1. Field of the Invention
The present invention relates to a ferroelectric random access memory and an operation method thereof. More specifically, the present invention relates to a ferroelectric random access memory, which is to be referred to as a 2T-1C FRAM, each cell of which is provided with two transistors (2T) and one ferroelectric capacitor (1C), and an operation method thereof.
2. Description of the Related Art
A conventional ferroelectric random access memory (FRAM) is based on switching of a ferroelectric capacitor. In a bistable polarization state, positive polarization is assigned as xe2x80x9c1xe2x80x9d and negative polarization is assigned as xe2x80x9c0xe2x80x9d. A novel concept is based on the charging and the discharging of a ferroelectric capacitor in conjunction with a p-n junction of CMOS transistors. This novel structure does not require switching. Therefore, the novel structure can avoid degradation issues such as fatigue and imprint. such as fatigue and imprint.
A conventional FRAM utilizes a bistable state of ferroelectric polarization, wherein positive polarization and negative polarization states are assigned as xe2x80x9c1xe2x80x9d and xe2x80x9c0xe2x80x9d, respectively, for memory logic. As long as the FRAM is switched to maintain bistable polarization states, reliability issues such as fatigue, imprint, impulse breakdown, and the like have made it difficult to fabricate reliable FRAM products.
A feature of the present invention is to provide a 2T-1C FRAM using the xe2x80x9cchargingxe2x80x9d and xe2x80x9cdischargingxe2x80x9d states of a ferrroelectric capacitor in conjunction with a p-n junction of CMOS transistors, to overcome degradation such as fatigue and imprint. An operation method thereof is also disclosed.
The present invention provides a 2T-1C ferroelectric random access memory comprising: a semiconductor substrate having a plurality of potential wells formed by doping it with first impurities; a plurality of memory cells each having two transistors and one capacitor; a plurality of connection lines electrically connecting the memory cells in the form of a matrix; and a plurality of dummy capacitors, wherein the two transistors include: a source formed by doping the semiconductor within each potential well with second impurities; a first drain and a second drain formed by doping the semiconductor within each potential well with the second impurities in a predetermined interval, respectively, so as to be arranged in line with the source in a first direction; a first gate formed on an insulation layer which is formed on a first channel between the source and the first drain; and a second gate formed on an insulation layer which is formed on a second channel between the first drain and the second drain, and wherein the one capacitor includes: a bottom electrode formed on an insulation layer which is formed on the source; a ferroelectric layer formed on the bottom electrode; and a top electrode formed on the ferroelectric layer, and wherein the connection lines include: first word lines connecting the first gates arranged in the first direction in each memory cell; bit lines connecting the first drains of the memory cells arranged in the second direction, which is perpendicular to the first direction, and to which the dummy capacitors are commonly connected; second word lines connecting the second gates of the memory cells arranged in the second direction; sensing lines connecting the second drains of the memory cells arranged in the second direction; contact plugs connecting the source and the bottom electrode in each cell; and plate lines connecting the top electrodes of the memory cells arranged in the second direction.
In a preferred embodiment of the present invention, the first impurities are xe2x80x9cpxe2x80x9d type impurities and the second impurities are xe2x80x9cn+xe2x80x9d type impurities. In an alternative embodiment, the first impurities may be xe2x80x9cnxe2x80x9d type impurities and the second impurities may be xe2x80x9cp+xe2x80x9d type impurities.
The sensing lines connecting the second drains of the memory cells may be arranged in the first direction.
The dummy capacitor may be formed between the bit line and the first drain of each cell.
Additionally, the present invention provides, a method for operating a 2T-1C ferroelectric random access memory comprising: a semiconductor substrate having a plurality of potential wells formed by doping it with first impurities; a plurality of memory cells each having two transistors and one capacitor; a plurality of connection lines electrically connecting the memory cells in the form of a matrix; and a plurality of dummy capacitors, wherein the two transistors include: a source formed by doping the semiconductor within each potential well with second impurities; a first drain and a second drain formed by doping the semiconductor within each potential well with the second impurities in a predetermined interval, respectively, so as to be arranged in line with the source in a first direction; a first gate formed on an insulation layer which is formed on a first channel between the source and the first drain; and a second gate formed on an insulation layer which is formed on a second channel between the first drain and the second drain, and wherein the one capacitor includes: a bottom electrode formed on an insulation layer which is formed on the source; a ferroelectric layer formed on the bottom electrode; and a top electrode formed on the ferroelectric layer, and wherein the connection lines include: first word lines connecting the first gates arranged in the first direction in each memory cell; bit lines connecting the first drains of the memory cells arranged in the second direction, which is perpendicular to the first direction, and to which the dummy capacitors are commonly connected; second word lines connecting the second gates of the memory cells arranged in the second direction; sensing lines connecting the second drains of the memory cells arranged in the second direction; contact plugs connecting the source and the bottom electrode in each cell; and plate lines connecting the top electrodes of the memory cells arranged in the second direction, the method comprising the steps of: (a) writing xe2x80x9c0xe2x80x9d state in a selected memory cell by applying a voltage Vw to the first word line and a voltage Vp to the plate line; (b) writing xe2x80x9c1xe2x80x9d state in a selected memory cell by applying a voltage Vw to the first word line and a voltage Vc to the second word line; and (c) reading the written state out by applying a voltage Vw to the first word line and a voltage Vc to the second word line and detecting negative charge at the selected memory cell.
In the step (c), the negative charge is detected at the selected memory cell via the sensing line connected to it. Also, in the step (c), if the negative charge is detected at the selected memory cell, the state of the selected memory cell is read out as xe2x80x9c0xe2x80x9d state. If the negative charge is not detected at the selected memory cell, the state of the selected memory cell is read out as xe2x80x9c1xe2x80x9d state. The step (c) may further comprise the step of restoring xe2x80x9c0xe2x80x9d state in the selected memory cell immediately after the selected memory cell is read out as xe2x80x9c0xe2x80x9d state, so that xe2x80x9c0xe2x80x9d state is maintained.